Join a forward-thinking team at Google Cloud, instrumental in developing cutting-edge custom silicon solutions that power Google's direct-to-consumer products. Your contributions will be vital to innovating products enjoyed by millions globally. You will play a key role in shaping next-generation hardware, ensuring exceptional performance, efficiency, and seamless integration.

As a Design Technology Co-Optimization (DTCO) Engineer, your role involves bridging process technology and product architecture to define advanced data center-class silicon. You will focus on maximizing process benefits by evaluating leading-edge logic nodes and novel transistor architectures. Through detailed Place and Route (P&R) experiments and sensitivity analyses, you will guide standard cell library architecture, metal stack configurations, and design rules. Close collaboration with Foundry, IP, and Architecture teams will be essential for identifying Power, Performance, and Area (PPA) challenges and driving System Technology Co-Optimization (STCO) initiatives. This includes executing sophisticated physical implementation studies, assessing the impact of scaling boosters, and creating automated methodologies for quantifying PPA improvements to ensure Google's hardware excels in efficiency and power density.

The AI and Infrastructure team is at the forefront of innovation, empowering Google customers with advanced capabilities and profound insights through AI and Infrastructure delivered at an unmatched scale, efficiency, reliability, and speed. Our reach extends to Googlers, Google Cloud clients, and billions of users worldwide.

We are the engine behind Google's transformative innovations, facilitating the creation of advanced AI models, providing immense computing power for global services, and offering the foundational platforms for future developer creations. Our teams, encompassing both software and hardware expertise, are defining the future of hyperscale computing, with dedicated groups working on TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and more.

Execute detailed Place and Route (P&R) experiments to assess the impact of advanced process features, library designs, and design rule variations on the Power, Performance, and Area (PPA) of data center-class IP.

Lead Design Technology Co-Optimization (DTCO) efforts by collaborating with foundries and internal technology teams to establish optimal metal stacks, track heights, and scaling boosters, such as backside power delivery and buried power rails.

Quantify process advantages through systematic benchmarking of logic and memory macros, pinpointing bottlenecks in power density and timing closure for upcoming node generations.

Develop automated physical design methodologies and workflows to accelerate technology exploration and enable swift "what-if" analyses for emerging transistor architectures.

Influence System Technology Co-Optimization (STCO) by partnering with Hardware Architects and Circuit Designers to translate process-level advancements into significant system-level performance enhancements.

Requires a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a closely related field, or equivalent practical experience.

Possesses 5 years of experience in Physical Design, specifically from Register-Transfer Level to Graphic Database System (RTL-to-GDS), or in technology development focused on advanced nodes like 7nm, 5nm, or smaller.

Demonstrates proficiency in scripting and automation using Tcl, Python, or Perl.