Join a pioneering team at Google Cloud, shaping the future of direct-to-consumer products with custom silicon solutions. You will contribute to innovations powering products used by millions globally, defining the next generation of hardware experiences for unparalleled performance, efficiency, and integration.

As a Design Technology Co-Optimization (DTCO) Engineer, your role is pivotal in bridging process technology and product architecture for cutting-edge data center-class silicon. You will maximize process potential by evaluating advanced logic nodes and novel transistor architectures. Through rigorous Place and Route experiments and sensitivity analysis, you will shape standard cell library architecture, metal stack designs, and design rules. Close collaboration with Foundry, IP, and Architecture teams is essential to pinpoint Power, Performance, and Area (PPA) bottlenecks and drive System Technology Co-Optimization (STCO) initiatives.

This role involves intricate physical implementation sweeps, assessing the impact of scaling boosters, and creating automated methodologies to quantify PPA gains, ensuring Google's hardware excels in efficiency and power density. The AI and Infrastructure team is at the forefront, empowering Google customers with advanced capabilities and insights through large-scale AI and Infrastructure delivery.

Execute high-fidelity Place and Route (P and R) experiments to assess the PPA impact of advanced process features, library architectures, and design rule variations on data center-class IP.

Drive Design Technology Co-Optimization (DTCO) through collaboration with foundries and internal technology teams to define optimal metal stacks, track heights, and scaling boosters like backside power delivery and buried power rails.

Quantify process entitlement via systematic benchmarking of logic and memory macros, identifying bottlenecks in power density and timing closure for next-generation nodes.

Develop automated physical design methodologies and flows to accelerate technology pathfinding and enable rapid "what-if" analysis of emerging transistor architectures.

Influence System Technology Co-Optimization (STCO) by partnering with Hardware Architects and Circuit Designers to translate process-level innovations into system-level performance gains.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience, is required.

We seek at least 5 years of experience in Physical Design (e.g., Register-Transfer Level- to-Graphic Database System (RTL-to-GDS)) or technology development focused on advanced nodes (e.g., 7nm, 5nm, or below).

Proficiency in scripting and automation using Tcl, Python, or Perl is essential for this role.

Preferred qualifications include a Master's degree or PhD in a relevant engineering or computer science field, with expertise in Complementary Metal-Oxide-Semiconductor (CMOS) device physics, FinFET/nanosheet architectures, and the impact of layout parasitics on PPA. Experience in DTCO, including standard cell library characterization, metal stack optimization, and evaluating scaling boosters, is highly valued. Familiarity with industry-standard tools for synthesis, place and route, static timing analysis, transistor-level design in advanced FinFET technology nodes, and SPICE simulations is beneficial. Additionally, experience working with major foundry technology files (PDKs) and interpreting Design Rule Manuals (DRM) to guide physical implementation is advantageous.