Join a pioneering team at Google Cloud dedicated to crafting custom silicon solutions that power the next generation of direct-to-consumer products. This role is pivotal in shaping the future of hardware, delivering exceptional performance, efficiency, and integration.

As a Design Technology Co-Optimization (DTCO) Engineer, you will integrate process technology with product architecture, defining cutting-edge data center silicon. Your work will focus on maximizing process potential by assessing advanced logic nodes and novel transistor architectures. Through rigorous Place and Route (P&R) experiments and sensitivity analyses, you'll directly influence standard cell library design, metal stack configurations, and design rules.

Collaboration is key, as you'll work closely with Foundry, IP, and Architecture teams to pinpoint Power, Performance, and Area (PPA) challenges. You will also champion System Technology Co-Optimization (STCO) initiatives by conducting detailed physical implementation sweeps, evaluating scaling boosters, and developing automated methodologies for quantifying PPA improvements. Ultimately, you will ensure Google's hardware achieves peak efficiency and power density.

Execute detailed Place and Route (P&R) experiments to assess the Power, Performance, and Area (PPA) impact of advanced process features, library designs, and design rule variations on data center-class IP.

Drive Design Technology Co-Optimization (DTCO) through close collaboration with foundries and internal technology groups to establish optimal metal stacks, track heights, and scaling boosters, such as backside power delivery and buried power rails.

Quantify process entitlement by systematically benchmarking logic and memory macros, identifying bottlenecks in power density and timing closure for next-generation nodes.

Develop automated physical design methodologies and workflows to expedite technology pathfinding and enable swift "what-if" analyses for emerging transistor architectures.

Influence System Technology Co-Optimization (STCO) by partnering with Hardware Architects and Circuit Designers to translate innovative process-level advancements into system-level performance enhancements.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a closely related discipline, or equivalent practical experience is required.

Possess at least 5 years of experience in Physical Design, spanning from Register-Transfer Level to Graphic Database System (RTL-to-GDS), or in technology development specifically focused on advanced nodes (e.g., 7nm, 5nm, or smaller).

Demonstrated experience with scripting and automation using languages such as Tcl, Python, or Perl.