Join a pioneering team at Google Cloud, driving innovation in custom silicon solutions that power Google's direct-to-consumer products. You will be instrumental in shaping the future of hardware, delivering exceptional performance, efficiency, and integration for products used by millions globally.

As a Design Technology Co-Optimization (DTCO) Engineer, you will bridge the gap between process technology and product architecture. Your role involves evaluating advanced logic nodes and emerging transistor architectures to unlock maximum process potential. You will conduct extensive Place and Route (P&R) experiments and sensitivity analyses, contributing to the optimization of standard cell libraries, metal stack definitions, and design rules.

Collaboration is key as you work closely with Foundry, IP, and Architecture teams to pinpoint Power, Performance, and Area (PPA) bottlenecks. You will champion System Technology Co-Optimization (STCO) initiatives by performing high-fidelity physical implementation sweeps, analyzing scaling booster impacts, and developing automated methodologies for quantifying PPA gains. Ultimately, you will ensure Google's hardware achieves peak efficiency and power density.

The AI and Infrastructure team is at the forefront of redefining possibilities, empowering Google customers with cutting-edge AI and infrastructure at an unprecedented scale. Our work supports Googlers, Google Cloud clients, and billions of users worldwide, driving breakthroughs in AI model development and global computing services.

Execute high-fidelity Place and Route (P&R) experiments to assess the PPA impact of advanced process features, library architectures, and design rule variations on data center-class IP.

Drive Design Technology Co-Optimization (DTCO) through collaboration with foundries and internal technology teams. Define optimal metal stacks, track heights, and scaling boosters, such as backside power delivery and buried power rails.

Quantify process entitlement by systematically benchmarking logic and memory macros. Identify bottlenecks in power density and timing closure for next-generation nodes.

Develop automated physical design methodologies and flows to accelerate technology pathfinding and enable rapid "what-if" analysis of emerging transistor architectures.

Influence System Technology Co-Optimization (STCO) by partnering with Hardware Architects and Circuit Designers to translate process-level innovations into significant system-level performance gains.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field is required, or equivalent practical experience.

Possess at least 5 years of experience in Physical Design (RTL-to-GDS) or technology development, with a focus on advanced nodes (7nm, 5nm, or below).

Proficiency in scripting and automation using languages such as Tcl, Python, or Perl is essential.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a specialization in computer architecture.

Experience with Complementary Metal-Oxide-Semiconductor (CMOS) device physics, FinFET/nanosheet architectures, and understanding the impact of layout parasitics on PPA is beneficial.

Familiarity with DTCO, including standard cell library characterization, metal stack optimization, and evaluating scaling boosters, is a plus.

Experience with industry-standard tools for synthesis, place and route, static timing analysis, transistor-level design in advanced FinFET technology nodes, and SPICE simulations is advantageous.

Working knowledge of major foundry technology files (PDKs) and interpreting Design Rule Manuals (DRMs) to guide physical implementation is preferred.