This role focuses on integrating testability features into chip designs during the initial phases. The primary goal is to ensure effective post-manufacturing chip testing by applying advanced DFT methodologies. You will play a crucial part in enhancing test coverage and detecting defects.

Collaboration with design and verification teams is key to optimizing test efficiency and achieving precise fault isolation. This position demands a proactive approach to problem-solving and a commitment to continuous improvement in the overall testing process throughout the chip's design lifecycle.

As a Design-For-Test Engineer, you are expected to become a subject matter expert and perform independently. Active participation and contribution in team discussions are essential, along with providing effective solutions to work-related challenges.

Key responsibilities include collaborating with cross-functional teams to align design and test strategies for optimal outcomes. You will continuously evaluate and implement new test methodologies to enhance product quality and effectively document and communicate test design processes and results to stakeholders.

A strong proficiency in Design for Testability (DFT) is a must-have for this position. Candidates should possess in-depth knowledge of scan chain insertion and optimization techniques, coupled with practical experience in Built-In Self-Test (BIST) architectures and boundary scan implementation.

Further requirements include the ability to analyze and troubleshoot issues related to test coverage and fault isolation. Familiarity with silicon validation and post-silicon debug processes is also expected. A minimum of 3 years of experience in DFT is mandatory, along with 15 years of full-time education.