Advance the effectiveness of post-manufacturing chip testing by integrating crucial testability features during the initial design phases. This role involves applying advanced DFT methodologies, including scan chains, Built-In Self-Test (BIST), and boundary scan, to precisely detect defects and significantly enhance test coverage. The primary goal is to ensure high-quality silicon by fostering close collaboration with design and verification teams, focusing on optimizing for test efficiency and accurate fault isolation.

As a Design-For-Test Engineer, your daily contributions will center on embedding robust testability elements directly into integrated circuit designs. This proactive approach aims to identify and address potential defects early in the lifecycle. Essential to this role is seamless collaboration with diverse teams to refine designs for superior fault detection and isolation, ultimately driving the production of exceptionally high-quality silicon chips. You will act as a vital link between the design and testing processes, significantly improving overall product reliability and performance.

Independently drive projects and develop expertise to become a Subject Matter Expert (SME). Actively contribute to team discussions and problem-solving sessions. Provide innovative solutions to complex work-related challenges. Collaborate closely with cross-functional teams to seamlessly integrate essential test features into chip designs. Analyze intricate test results, providing crucial feedback to refine designs and boost test coverage. Mentor and support junior team members by sharing knowledge and offering assistance with problem-solving. Stay current with evolving design complexities by continuously updating and refining test methodologies.

A strong command of Design for Testability (DFT) is essential. Proven experience in implementing scan chains, Built-In Self-Test, and boundary scan techniques. A deep understanding of various fault models and the principles of test pattern generation. Demonstrated ability to collaborate effectively with design and verification teams to optimize test structures. Familiarity with silicon debug and failure analysis processes. Proficiency with industry-standard EDA tools commonly used for DFT implementation and verification. Minimum of 3 years of dedicated experience in Design for Testability (DFT). A prerequisite of 15 years of full-time education is required.