This role focuses on enhancing post-manufacturing chip testing by integrating essential testability features during the design phase. You will apply advanced DFT methodologies like scan chains, Built-In Self-Test (BIST), and boundary scan to effectively detect defects and achieve high test coverage. Collaboration with design and verification teams is key to optimizing test efficiency and fault isolation, ensuring high-quality silicon output.

- Independently tackle challenges and aim to become a subject matter expert. - Actively participate and contribute to team discussions and problem-solving. - Provide effective solutions for work-related issues. - Seamlessly integrate testability features by working closely with cross-functional teams. - Continuously refine test methodologies to boost fault coverage and reduce testing duration. - Document DFT strategies and findings to foster knowledge sharing and process enhancement.

- A minimum of 3 years of dedicated experience in Design for Testability (DFT). - Strong expertise in scan chain insertion and optimization techniques. - Practical experience with Built-In Self-Test (BIST) implementation and adherence to boundary scan standards. - Ability to collaborate with design and verification teams to improve test coverage and fault isolation. - Familiarity with silicon debug and failure analysis processes is beneficial. - Completion of 15 years of full-time education is mandatory.