Join a pioneering team crafting custom silicon solutions that define the future of Google's direct-to-consumer products. Your contributions will drive innovation in hardware experiences, delivering exceptional performance, efficiency, and integration for products used by millions globally. This role focuses on verifying next-generation RISC-V processor cores, ensuring the high quality of advanced architecture features and ISA extensions.

The team operates within Google's broad computing software platforms and first-party devices, integrating cutting-edge AI, software, and hardware. We are dedicated to researching and developing new technologies that make user interactions with computing faster and more seamless, building globally impactful and innovative experiences.

Collaborate closely with designers, architects, and stakeholders to develop comprehensive test plans, identify dependencies, and define deliverables.

Plan the verification of RISC-V CPU cores and associated peripherals by thoroughly understanding design specifications and engaging with architecture and design engineers to pinpoint critical verification scenarios.

Work in tandem with Architecture, software, and design teams to drive key technical decisions. Develop and refine constrained-random verification environments using System Verilog and UVM.

Actively represent Design Verification status throughout the development lifecycle. Take ownership of technical decisions, ensuring project momentum, and setting goals for IP verification methodology. Identify and implement methodology improvements.

Partner with Pre-Silicon (Si) and Post-Si Validation teams to ensure the successful bring-up of the IP.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience, is essential.

Requires a minimum of 10 years of experience in verifying IPs, Subsystems, and SoCs. You should also have 8 years of experience in developing design verification strategies and plans, along with proficiency in constrained-random verification using SystemVerilog (SV) and Universal Verification Methodology (UVM).

Demonstrated expertise in verifying multi-stage, high-performance CPU cores and related peripherals, as well as a strong understanding of RISC-V architecture and ISA extensions, is required (8 years of experience).

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a specialization in computer architecture. Experience with low power design, debug, performance verification, use case verification, and security IP/subsystems is also advantageous. Familiarity with scripting languages such as Python, Perl, or Tcl, and an interest in AI-assisted IP Verification Methodologies, would be beneficial.