Join a pioneering team at Google Cloud, driving innovation in custom silicon solutions for direct-to-consumer products. Your expertise will be instrumental in shaping the next generation of hardware, delivering exceptional performance, efficiency, and integration for products used by millions globally. This role offers a unique opportunity to influence the future of AI/ML hardware acceleration and contribute to cutting-edge TPU technology.

You will collaborate closely with foundry partners and internal technology, circuits, physical design, and front-end teams. Your mission will be to overcome the limitations of Moore's Law and deliver state-of-the-art ASICs and SoCs. By identifying optimal process nodes, methodologies, and IPs, you will ensure the development of competitive and reliable products.

Lead technical evaluations of advanced process nodes, defining strategies for custom circuits and memories to achieve dynamic PPA targets. Engage with foundry partners to obtain and debug necessary collaterals for design kits, standard cells, and IPs. Provide technical mentorship to circuit and physical design teams, guiding the design and verification of custom circuits and assessing performance and power metrics. Define optimal methodologies by analyzing performance, power, and area across various technology nodes and implementation techniques. Enhance library cells and metal interconnects for improved PPA. Collaborate with integrated teams to ensure seamless integration of standard cell libraries and memories in advanced CMOS nodes, evaluating the impact of new PDK releases.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, coupled with equivalent practical experience, is required. You should possess 15 years of experience spanning process technology, circuit design, and physical design.

Your background must include experience with process technology nodes, encompassing yield and reliability, design kits, IP collaterals, and evaluating power, performance, and area. Proficiency in transistor-level design within FinFET nodes for standard cells and memories/SRAMs, including SPICE simulations or characterization methodologies, is essential. Experience with concurrent optimization across custom circuit/IP and physical design spaces is also a key requirement.