Shape the future of AI/ML hardware acceleration by driving cutting-edge TPU technology for Google's most demanding applications. Join a team that develops custom silicon solutions powering Google's direct-to-consumer products and influence the next generation of hardware.

Collaborate with foundry partners and internal technology, circuit, and physical design teams to deliver state-of-the-art ASICs and SoCs. Identify optimal process nodes, methodologies, and IPs to ensure competitive and reliable products.

Support the on-time delivery of design kits, IPs, and related collaterals. Develop and mature novel high-performance computing design methodologies, seeing them through from inception to tapeout.

Lead technical evaluations of advanced process nodes, setting strategy for custom circuits and memory/SRAMs to meet dynamic PPA targets. Engage with foundry partners to obtain and debug necessary collaterals for design kits, standard cells, and IPs.

Provide technical mentorship to circuit and physical design teams, overseeing custom circuit design and verification. Drive circuit-level assessments for performance and power metrics. Define optimal methodologies by investigating performance, power, and area across various technology nodes and implementation techniques. Enhance library cells and metal interconnects for improved PPA.

Collaborate with circuits, physical design, logic design, and technology teams on advanced CMOS nodes. Ensure seamless integration of standard cell libraries and memories/SRAMs. Evaluate the impact of new PDK releases.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience, is required. Possess 15 years of experience in process technology, circuit design, and physical design.

Demonstrated experience with process technology nodes, including yield, reliability, design kits, IP collaterals, and evaluating power, performance, and area. Expertise in transistor-level design within FinFET nodes for standard cells and memories/SRAMs, including SPICE simulations or characterization methodology.

Proficiency with concurrent optimization across custom circuit/IP and physical design spaces. A Master's degree or PhD in Electrical Engineering, along with experience in programming/scripting (Python, TCL), is preferred. Proven technical leadership, guiding teams through design and tapeout, and interfacing with foundry suppliers is highly valued. Strong understanding of semiconductor device physics and transistor characteristics, alongside a track record of delivering circuit and physical design solutions leading to product tapeout, are also preferred.