Join NVIDIA, a leader in GPU and SOC development, as a Chip Power Estimation Engineer. This role focuses on architecting and refining advanced power models for cutting-edge chips. You'll gain deep insights into high-level chip architecture, application use-cases, and low-power design techniques.

This is a unique opportunity to significantly impact product lines spanning consumer graphics, autonomous vehicles, and AI. Become part of a global team dedicated to pushing technological boundaries and shaping the future of computing. At NVIDIA, we are driven by a passion for parallel and visual computing, transforming complex challenges through GPU technology.

Architect, develop, and correlate power estimation models and tools for NVIDIA's innovative chips.

Design and build power models for various use-cases, including idle power and I/O power.

Contribute to the creation and testing of estimation infrastructure and tools.

Calibrate and validate power models using actual silicon data.

Analyze and influence chip configuration and process technology choices to enhance power and performance.

Investigate and propose Performance/Watt improvement strategies for NVIDIA GPUs and SOCs.

Possess a B.Tech. or M.Tech. degree with at least 2 years of experience in Power/Performance estimation and optimization.

Exhibit strong fundamental knowledge of power characteristics, including transistor-level leakage and dynamic behavior in VLSI circuits.

Familiarity with low-power design techniques such as multi VT, clock gating, power gating, and DVFS is essential.

Demonstrate a robust understanding of power estimation techniques, methodologies, and algorithms.

Proficiency in programming, with a preference for Python, and strong object-oriented design skills.

Exposure to lab setups, power measurement equipment, and board-level power analysis is advantageous.

Experience with power analysis EDA tools like PTPX/EPS is a plus, as are excellent communication and teamwork abilities.