Join NVIDIA's dynamic Clocks Team as a Senior ASIC Verification Engineer. We are at the forefront of developing high-quality clocking and reset logic for advanced SOCs in automotive and datacenter applications. As our designs grow in complexity, innovative and sophisticated verification is crucial to ensure bug-free delivery for products ranging from data centers and consumer graphics to self-driving cars and AI. We seek creative, curious, and motivated individuals passionate about technology to contribute to our world-class engineering teams.

Our work requires cutting-edge clocking verification solutions that are not only innovative and ensure design quality but also balance infrastructure, reusability, testing speed, and multi-platform support.

You will own the end-to-end validation of Clocking structures for Tegra automotive and datacenter products. This includes developing comprehensive test plans, automating validation flows, defining coverage metrics, executing tests, identifying and resolving bugs, and contributing to productization.

You will tackle complex challenges, developing scalable solutions that ensure cross-platform compatibility. This role involves hands-on experience with industry-standard tools and state-of-the-art verification methodologies, including System Verilog, UVM, C++, Perl, and Python, alongside NVIDIA's custom tools. Close collaboration with clock architecture and design teams, as well as coordination with internal and external teams across time zones, is essential.

We are looking for engineers with a BS or MS in EE/ECE or equivalent experience, coupled with over 3 years of relevant industry work experience. A strong understanding of logic design and architecture is necessary.

Essential expertise includes industry-standard verification flows such as SV constraint random verification, UVM, Formal Verification, coverage metrics, profiling tools, and X prop. Experience with both block-level and system-level verification is required. Strong coding skills in System Verilog, scripting languages (Perl/Python), and C++ are critical. The ability to collaborate effectively across multiple groups and prior experience implementing test plans for pre-silicon platforms are also key. Understanding of DFT/IST is considered optional.