Join NVIDIA's innovative Clocks Team as a Senior ASIC Verification Engineer. We are dedicated to delivering high-quality clocking and reset logic for advanced SOCs in automotive and datacenter applications. As our designs grow in complexity, we seek experts to ensure bug-free clock designs that power cutting-edge products, from data centers to AI.

Our team is committed to developing innovative verification solutions. These solutions must uphold quality, cover complex design specifications, and balance infrastructure constraints with reusability, testing speed, and multi-platform support.

Take ownership of validating clocking structures for Tegra automotive and datacenter products throughout the entire lifecycle. This includes developing comprehensive test plans, creating automation, building validation flows, defining coverage metrics, executing tests, resolving bugs, and ensuring product readiness.

You will tackle complex challenges by developing scalable, cross-platform solutions. You'll utilize industry-standard tools and cutting-edge verification methodologies, including coding in System Verilog, UVM, C++, Perl, and Python.

Collaborate closely with our clock architecture and design teams to rigorously validate our clock designs. Effective coordination with internal and external teams across different time zones is also essential.

We require a BS or MS in Electrical Engineering/Electronics and Communication Engineering or equivalent experience, along with a minimum of 3 years of relevant industry work experience. A strong understanding of logic design and architecture is crucial.

Expertise in industry-standard verification flows such as SV constraint random verification, UVM, Formal Verification, coverage metrics, profiling tools, and X prop is essential. Experience with block-level and system-level verification is also expected.

Candidates must possess strong coding skills in System Verilog, scripting languages like Perl/Python, and C++. The ability to collaborate effectively across multiple groups and prior experience in implementing test plans for pre-silicon platforms are key. Familiarity with DFT/IST is considered a plus.