NVIDIA is a leader in transforming computer graphics, PC gaming, and accelerated computing. With a legacy of innovation spanning over 25 years, we are now at the forefront of AI, defining the next era of computing. Our GPUs are becoming the brains for intelligent systems, from computers and robots to self-driving cars. Join our diverse and supportive environment where you can make a lasting impact and do your best work.

As a key methodology engineer, you will drive design methodology, automation, and integration for our High-Speed IO team. Responsibilities include owning the integration process, defining and implementing best-in-class methodologies across global teams, and building modular, reusable infrastructure. You will manage full-chip and block-level integration, stitch RTL units, define design methodologies for improved scalability and quality, and build automation pipelines using Python/Perl. Collaboration with RTL, verification, physical design, and architecture teams is essential for flow compatibility and design readiness. You will also drive full-chip debug efforts, contribute to internal standards improvement, and mentor engineers on flow usage.

We require a BS or B.Tech, or MS or M.tech in EE, ECE, CS, or an equivalent degree, coupled with a minimum of 2 years of experience in ASIC design integration and methodologies. A comprehensive understanding of IP development flows and build flows is mandatory. Excellent influencing skills for cross-cultural collaboration, strong debugging, analytical, and problem-solving abilities are essential. Great interpersonal skills and the capacity to excel as a team player are also important. Experience with AI tools like Claude and Cursor is a plus.