Join a pioneering team at Google, dedicated to crafting custom silicon solutions that drive the future of our direct-to-consumer products. Your contributions will be instrumental in innovating hardware experiences that reach millions worldwide, delivering exceptional performance, efficiency, and seamless integration. This role is a key part of the Platforms and Devices group, shaping the next generation of computing platforms and first-party devices powered by Google AI, software, and hardware.

We are focused on researching, designing, and developing groundbreaking technologies to enhance user interaction with computing, making it faster and more intuitive across desktop, mobile, and application environments.

Own the signoff for complex logic blocks and subsystems, collaborating closely with Physical Design teams on IR/Electromigration (EM) to ensure silicon quality meets functional, manufacturing, and PPA targets. Drive convergence for PG (Power and Ground) bump assignments, Redistribution Layer (RDL) routing, IR (Static, Dynamic), EM, and Inrush for multiple IPs using industry-standard analysis tools.

Lead Electrostatic Discharge (ESD) convergence for Google IPs by applying fundamental ESD concepts and utilizing DEF-based tools. Propose and implement changes to PG Grids, flows, and methodologies, working with internal experts, technology teams, CAD, and EDA partners to resolve tool issues. Develop scripts to enhance convergence, streamline debugging, and conduct in-depth analysis. Mentor junior engineers and interns in achieving convergence and adopting new methodologies.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience, is required. Candidates should possess at least 4 years of experience in Power Delivery Network (PDN) convergence at the IP/SOC level, CAD/EDA tool support, or PDN methodology.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a specialization in computer architecture. Experience with Power Grid design, PG bump assignments, RDL optimizations, and convergence analysis for IR, EM, ESD, and Inrush is highly valued. A solid understanding of IR methodology and relevant EDA tools is also beneficial.