Join NVIDIA, a company at the forefront of innovation in GPUs, AI, and high-performance computing. We are seeking a talented ASIC STA Engineer to contribute to the development of industry-leading high-speed communication devices designed for AI platforms. Become part of a dynamic and professional environment where you will significantly impact cutting-edge technology and amplify human creativity and intelligence. Experience a diverse and supportive culture that inspires excellence.

As an ASIC STA Engineer, you will manage full chip and chiplet-level STA convergence from initial stages through signoff. Your role includes participating in top-level floor plan and clock planning, optimizing signoff flows with CAD teams, and integrating timing for digital partitions and analog IPs. You will provide crucial feedback to Physical Design (PD) and RTL teams and collaborate closely with logic design and DFT engineers to define and refine constraints for optimal runtime and efficiency.

We are looking for candidates with a B.SC. or M.SC. in Electrical Engineering or Computer Engineering, possessing at least 3 years of experience in physical design and STA. Proven expertise in RTL2GDS and STA design convergence is essential, along with familiarity with physical design EDA tools like Synopsys and Cadence. A strong track record in hands-on STA from early stages to signoff using Synopsys Primetime, coupled with deep knowledge of timing concepts, is required. Excellent teamwork and communication skills are highly valued.