Join a forward-thinking team dedicated to crafting custom silicon solutions that will define the future of Google's consumer products. Your work will be instrumental in developing next-generation hardware experiences, driving unparalleled performance, efficiency, and seamless integration for products used by millions globally.

The AI and Infrastructure team is at the forefront of innovation, empowering Google users with advanced capabilities and insights. We achieve this by delivering AI and Infrastructure at immense scale, optimizing for efficiency, reliability, and speed. Our impact reaches Googlers, Google Cloud clients, and billions of users worldwide.

We are the engine behind Google's pioneering advancements. Our teams fuel the development of cutting-edge AI models, provide immense computing power for global services, and build the foundational platforms for developers. From software to hardware, we are shaping the future of hyperscale computing, with key initiatives focusing on TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, and systems research.

Develop comprehensive architecture specifications tailored to meet current and future AI/ML computing demands. Create and refine architectural and microarchitectural power/performance models. Conduct rigorous quantitative and qualitative performance and power analyses.

Foster collaborative partnerships with hardware design, software, compiler, Machine Learning (ML) model, and research teams to achieve effective hardware/software co-design and optimize performance. Evaluate diverse silicon solutions for Google’s data center AI accelerator roadmap, including components, vendor collaborations, custom designs, and chiplets.

Establish and maintain high-performance hardware/software interfaces. Work closely with stakeholders in software, verification, emulation, physical design, packaging, and silicon validation to ensure the integrity, correctness, and performance of designs.

Take ownership of the microarchitecture for designated compute blocks and subsystems. Proactively identify and implement improvements in power, performance, and area for your owned modules. Contribute to the development and enhancement of simulation tools.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related discipline, or equivalent practical experience is required. Candidates should possess at least 4 years of experience in architecture and micro-architecture design for graphics, Machine Learning (ML), or in managing low-precision/mixed-precision numerics, vector processors, DSP processors, or architecting networking ASICs.

Demonstrated expertise in memory hierarchy, memory controllers, HBM, and DRAM technologies is essential. A Master's or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science, with a specialization in computer architecture, is preferred.

Additional preferred qualifications include experience collaborating with software teams on hardware/software interface optimization. Experience in performance estimation through analysis, modeling, and network simulation, as well as defining and driving performance test plans, is highly valued. Proficiency in programming languages such as C++ and Python is beneficial.

Familiarity with arithmetic units, bus architectures, accelerators, memory hierarchies, and high-performance, low-power design techniques is advantageous.