Shape the future of Google's direct-to-consumer products by developing custom silicon solutions. Join a pioneering team that pushes technological boundaries, contributing to innovations that impact millions globally. Your expertise will define next-generation hardware, delivering exceptional performance, efficiency, and seamless integration.

The AI and Infrastructure team is at the forefront of innovation, empowering Google customers with advanced capabilities and insights. We deliver AI and Infrastructure at an unmatched scale, maximizing efficiency, reliability, and speed. Our services cater to internal Googlers, external Google Cloud customers, and billions of users worldwide.

We are the engine behind Google's transformative advancements, facilitating the creation of cutting-edge AI models, providing immense computing power for global services, and establishing foundational platforms for developers. Across software and hardware, our teams are instrumental in shaping world-leading hyperscale computing. Key areas include TPU development, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, and systems research.

Develop comprehensive architecture specifications to address current and future AI/ML computing needs. Create power/performance models and microarchitecture designs, evaluating quantitative and qualitative performance metrics.

Foster strong collaborations with hardware design, software, compiler, ML model, and research teams to ensure effective hardware/software co-design and high-performance interfaces. Assess various silicon solutions for Google's data center AI accelerator roadmap, including components, vendor collaborations, custom designs, and chiplets.

Establish and optimize high-performance hardware/software interfaces. Work closely with software, verification, emulation, physical design, packaging, and silicon validation teams to guarantee design completeness, correctness, and performance.

Take ownership of microarchitecture for compute blocks and subsystems, driving power, performance, and area enhancements. Contribute to the development and improvement of simulation tools.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, coupled with equivalent practical experience, is required. Possess at least 4 years of experience in areas such as architecture and micro-architecture design for graphics, Machine Learning (ML), or managing low-precision/mixed-precision numerics, vector processors, DSP processors, or architecting networking ASICs.

Demonstrated experience with memory hierarchies, memory controllers, HBM, and DRAM technologies is essential.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a specialization in computer architecture. Experience working with software teams to optimize hardware/software interfaces is highly beneficial. Proficiency in estimating performance through analysis, modeling, and network simulation, as well as defining and driving performance test plans, is desirable.

Familiarity with programming languages like C++ and Python, along with knowledge of arithmetic units, bus architectures, accelerators, memory hierarchies, and high-performance/low-power design techniques, will strengthen your application.