Join a pioneering team shaping Google's future consumer products through custom silicon development. Your contributions will drive the next era of hardware, delivering exceptional performance, efficiency, and integration for millions of users. This role is within the AI and Infrastructure team, dedicated to advancing AI and infrastructure capabilities at an unprecedented scale, benefiting Google users, Cloud customers, and internal teams.

We are at the forefront of Google's technological advancements, powering AI model development, providing immense computing power for global services, and building the foundational platforms for developers. Our work spans software and hardware, including TPUs, Vertex AI, Google Global Networking, Data Center operations, and systems research, collectively defining the future of hyperscale computing.

Develop comprehensive architecture specifications aligned with current and future AI/ML roadmaps. Create and evaluate power/performance models, alongside microarchitectural designs, conducting thorough quantitative and qualitative analyses.

Collaborate closely with hardware design, software, compiler, Machine Learning (ML), and research teams to enable effective hardware/software co-design and optimize high-performance interfaces. Evaluate diverse silicon solutions for Google’s data center AI accelerator roadmap, including components, vendor partnerships, custom designs, and chiplets.

Drive the microarchitecture of compute blocks and subsystems, identifying and implementing improvements in power, performance, and area. Contribute to the development of simulation tools and ensure seamless integration with verification, emulation, physical design, packaging, and silicon validation teams for design completeness and performance.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related discipline, or equivalent practical experience is required. Four years of specialized experience is needed in areas such as architecture and micro-architecture design for graphics, Machine Learning (ML), managing low-precision or mixed-precision numerics, vector processors, DSP processors, or architecting networking ASICs.

Demonstrated experience with memory hierarchy, memory controllers, High Bandwidth Memory (HBM), and Dynamic Random-Access Memory (DRAM) technologies is essential. Preferred qualifications include a Master's or PhD in a relevant engineering or computer science field with a focus on computer architecture, alongside experience in optimizing hardware/software interfaces with software teams.

Expertise in performance estimation through analysis, modeling, and network simulation, including driving performance test plans, is beneficial. Proficiency in programming languages like C++ and Python, along with knowledge of arithmetic units, bus architectures, accelerators, memory hierarchies, and high-performance, low-power design techniques, will further strengthen your candidacy.