Join a pioneering team focused on creating custom silicon solutions that will drive the future of Google's consumer products. Your contributions will be instrumental in shaping next-generation hardware, delivering exceptional performance, efficiency, and seamless integration for millions of users.

The AI and Infrastructure team is at the forefront of innovation, enabling Google customers with advanced capabilities and insights through AI and Infrastructure delivered at an unmatched scale, efficiency, and reliability. This includes empowering Googlers, Google Cloud clients, and billions of Google users globally.

We are the engine behind Google's significant advancements, fueling the development of state-of-the-art AI models, providing immense computing power for global services, and offering the foundational platforms for developers to build the future. Our teams, spanning software and hardware, are actively shaping the landscape of world-class hyperscale computing, with key initiatives in TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, and systems research.

Define architecture specifications tailored to meet current and future AI/ML computing demands. Develop and refine architectural and microarchitectural power/performance models, and conduct thorough quantitative and qualitative analyses.

Engage in hardware/software co-design with hardware design, software, compiler, ML model, and research teams to establish high-performance interfaces. Evaluate diverse silicon solutions, including vendor collaborations, custom designs, and chiplets, to support Google's data center AI accelerator roadmap.

Create and optimize high-performance hardware/software interfaces. Work closely with verification, emulation, physical design, packaging, and silicon validation teams to ensure the integrity and performance of designs.

Take ownership of the microarchitecture for compute blocks and subsystems, focusing on identifying and implementing power, performance, and area enhancements. Contribute to the development and enhancement of simulation tools.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline, alongside equivalent practical experience, is required. Candidates should possess a minimum of 4 years of experience in areas such as architecture and micro-architecture design for graphics, Machine Learning (ML), managing low-precision or mixed-precision numerics, vector processors, DSP processors, or architecting networking ASICs.

Familiarity with memory hierarchy, memory controllers, HBM, and DRAM technologies is essential. A Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a specialization in computer architecture, is preferred. Experience in collaborating with software teams to optimize hardware/software interfaces and in performance estimation through analysis, modeling, and simulation is also desirable.

Proficiency in programming languages like C++ and Python is beneficial, as is knowledge of arithmetic units, bus architectures, accelerators, memory hierarchies, and techniques for high-performance and low-power design.