Drive the technical strategy and architecture for cutting-edge AI/ML acceleration silicon. This role involves defining the core components, including compute engines, memory systems, and interconnects, while ensuring robust software enablement. Focus on advancing the NPU/Matrix Engine/MAC architecture and optimizing memory hierarchies to meet demanding AI workload requirements.

This is an opportunity to lead the AI accelerator roadmap and create differentiated solutions. You will play a crucial role in supporting customer engagements and technical workshops, translating complex needs into effective silicon designs.

Lead the architectural design of AI accelerators, from high-level strategy to detailed implementation. Analyze AI workloads to define optimal mapping strategies and drive key architectural decisions for NPU, Matrix Engine, and MAC units. Define the memory hierarchy, ensuring sufficient bandwidth and low latency. Guide RTL and verification teams throughout the development lifecycle. Support customer technical workshops and contribute to solution definition. Drive the accelerator roadmap, focusing on innovation and competitive differentiation.

A seasoned professional with over 15 years of experience in ASIC/SoC design. Proven track record in AI, GPU, DSP, NPU, TPU, or HPC silicon is essential. Deep understanding of AI workloads and inference pipelines is required. Expertise in compute architecture and memory systems, such as ARM Neoverse or RISC-V mesh-based compute sub-systems, is highly valued. Experience with complex NoC designs (e.g., Arteris/ARM) and knowledge of other processors like ARM A, M, and R series are beneficial. Familiarity with RTL design and verification methodologies is necessary. Performance modeling experience using virtual or emulation platforms is key. Strong customer-facing capabilities are a must.